1. Field of the Invention
The invention relates to programmable devices and in particular to testing of combinatorial logic in a functional logic block, for example, in an unprogrammed field-programmable gate array (FPGA) or in an unprogrammed programmable application specific integrated circuit (pASIC).
2. Background of the Invention
A programmable device is a versatile integrated circuit chip, the internal circuitry of which may be configured by an individual user to realize a user-specific circuit. A programmable device includes configurable logic sometimes referred to as a field-programmable gate array (FPGA), a programmable application specific integrated circuit (pASIC), a logic cell array (LCA), a programmable logic device (PLD), and a complex programmable logic device (CPLD). To configure a programmable device, the user configures an on-chip interconnect structure of the programmable device so that selected input ports and selected output ports of selected on-chip circuit components are electrically connected together in such a way that the resulting circuit is the user-specific circuit desired by the user.
In a programmable device employing, for example, amorphous silicon antifuses, selected amorphous silicon antifuses disposed between selected wire segments are “programmed” to electrically connect together the selected wire segments. Which antifuses are programmed and which antifuses are left unprogrammed determines how the circuit components are interconnected and therefore determines the resulting functionality of the circuit. For background information on programmable devices employing antifuses, see, e.g.: U.S. Pat. No. 5,424,655 entitled “Programmable application specific integrated circuit employing antifuses and methods therefor”; U.S. Pat. No. 5,825,201 entitled “Programming architecture for a programmable integrated circuit employing antifuses”; and U.S. Pat. No. 6,426,649 entitled “Architecture for field programmable gate array.” The contents of these documents are incorporated herein by reference in their entirety.
The semiconductor industry is driven with a desire to provide higher levels of integration. With higher levels of integration, silicon space and cost are reduced while performance and reliability are increased. Unfortunately, higher levels of integration lead to greater specificity. For example, application specific integrated circuits (ASICs) are highly specific devices that often serve the needs of only one customer. Programmable logic devices, such as field programmable gate arrays (FPGAs) are versatile integrated circuit chips, which have internal circuitry logic with user selected connections that a user can configure to realize user-specific functions. While programmable logic is versatile, there are significant design challenges in size, routing, pin-out stability when mapping large complex functions onto a silicon platform containing programmable logic.
A programmable device may include a plurality of functional logic blocks having combinatorial logic which a user uses as fundamental building blocks to realize a desired circuit. Consequently, what is needed is a single integrated device that combines the flexibility of programmable logic with the performance and reliability of a dedicated device but also allows for more complete testing of combinatorial logic within each functional logic block. Therefore, it is desirable to provide testing structures and methods to effectively test combinatorial circuitry in a functional logic block prior to permanent programming of antifuses by an end-user.